The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device incorporating a ferroelectric capacitor.
These days, semiconductor memories are widely used to serve as main memories of large-scale computers, personal computers, home electric appliances, portable telephones and the like. The types of the semiconductor memories include volatile DRAM (Dynamic RAM), SRAM (Static RAM), nonvolatile MROM (Mask ROM) and EEPROM (Electrically Erasable Programmable ROM) and the like. In particular, the DRAM has advantages of a low cost characteristic (the area of the cell is 1/4 of that of the SRAM) and high speed (as compared with the EEPROM). Therefore, the DRAM, at present, commands the substantially overall share of the market though the DRAM is a volatile memory.
Although the rewritable nonvolatile EEPROM permits shutoff of the power supply because it is the nonvolatile memory, the EEPROM suffers from an undesirably small rewriting number of times (the number of W/E) of about 10.sup.6. Moreover, writing requires a long time of about a microsecond and a high voltage (12V to 22V) must be applied to perform writing. The foregoing problems result in that the obtained market is smaller than that obtained by the DRAM.
On the other hand, the nonvolatile memory FRAM (Ferroelectric RAM) incorporating a ferroelectric capacitor (Ferroelectric Capacitor) suggested in 1980 has the following advantages: the FRAM is a nonvolatile memory. Moreover, the rewriting number of times is 10.sup.12, time required to read/write data is substantially the same as that required for the DRAM and required operating voltage of 3V to 5V. Therefore, there is possibility that the foregoing memory is substituted for the overall memory market. Therefore, a multiplicity of manufacturers is developing the FRAM. At present, 1 Mb FRAM is disclosed at the academic level (H. Koike et al., 1996 IEEE Internal Solid-Stable Circuit Conference Digest of Technical Paper, pp. 368-369, Feb. 1996). The cell size of the developed FRAM cell is reduced from a developed size of the SRAM+SM (Shadow Memory) structure to a 2-transistor+2-capacitor structure. Thus, the simplification and fining of the cell structure has caused the cell size to be reduced.
FIG. 1A shows an equivalent circuit of a memory cell of a conventional FRAM having a 1-transistor+1-capacitor structure. The memory cell having the 1-transistor+1-capacitor structure is similar to the 1-transistor+1-capacitor structure of the DRAM in which the transistor and the capacitor are connected to each other in series. The DRAM incorporates a paraelectric capacitor as the capacitor thereof, while the FRAM incorporates a ferroelectric capacitor having a hysteresis characteristic. Therefore, a cell array structure similar to that of the DRAM is employed, that is, a folded BL structure is employed. As shown in FIG. 1B, which is a sectional view, the minimum cell size is 2F.times.4F=8F.sup.2. The foregoing size cannot easily be reduced. Note that symbol F represents a minimum machining size.
As an example of forcible realization of 4F.sup.2 size, structures for realizing the 4F.sup.2 size by using a stacked-type transistor or a stacked-type TFT (Thin Film Transistor) exist. The foregoing structure cannot easily be manufactured. A structure is suggested in which cell transistors are connected to one another in series. Moreover, a capacitor is connected each of the cell transistors and the plate electrode. Thus, a size similar to the 4F.sup.2 size is realized (a NAND cell). The foregoing structure has suffered from poor general versatility because random access cannot be performed.
As described above, the conventional FRAM cell has a first problem in that the following three requirements cannot simultaneously be met: (1) obtaining a memory cell having a small size of 4F.sup.2 ; (2) obtaining a planar transistor which can easily be manufactured; and (3) realizing a random access function having general versatility.
As for the operating method, the DRAM is structured such that a plate electrode disposed at one end of the capacitor is fixed to (1/2)Vdd. The FRAM is structured such that variation between 0V to Vdd is performed. The two types of the memories are different from each other in only the foregoing fact. The foregoing structure is changed from the method of varying the plate electrode as shown in FIG. 1C (T. Sumi et al., 1994 IEEE International Solid-State Circuit Conference Digest of Technical Paper, pp. 268-269, Feb, 1994 and the like) to the structure as shown in FIG. 1D in which fixation to (1/2)Vdd is performed (H. Koike et al., 1996 IEEE international Solid-State Circuit Conference Digest of Technical Paper, pp. 368-369, Feb, 1996 and K. Takeuchi et al, IEICE Trans, Electron., Vol. E79-C, No. 2, Feb, 1996).
The method of driving the plate electrode from 0V to Vdd suffers from an excessively long driving time because a number of memory cells are connected to the plate electrode and, therefore, a great load capacity is required. As compared with the conventional DRAM, the operation speed in both of the access time and the cycle time is reduced under present circumstances. The method of fixing the plate to (1/2)Vdd is not required to drive the plate having a large load capacity. Therefore, access time and cycle time similar to those obtained from the DRAM can be realized.
The conventional FRAM memory cell has a structure similar to that of the DRAM such that the transistor and the ferroelectric capacitor are connected to each other in series. Therefore, as shown in FIG. 1D which is a circuit diagram, the storage node (SN) is floated at the time of standby after the power is turned on. Therefore, data "1" is stored in the SN, the SN is lowered to Vss owning to a junction leak of the pn-junction of the cell transistor. It leads to fact that information in the cell is destroyed when the plate electrode is fixed to (1/2)Vdd. Therefore, the (1/2)Vdd cell plate method is required to perform a refreshing operation similar to that for the DRAM. Thus, there arise problems in that greater power is required and a severer specification is required to prevent leakage from the cell. As a result, manufacture cannot easily be performed.
As described above, the conventional FRAM has a second problem in that both of the high-speed operation (fixation of the PL potential) and elimination of the refreshing operation cannot simultaneously be realized.
To overcome the first and second problems, the inventors of the present invention has suggested a semiconductor memory device which is a nonvolatile ferroelectric memory which is capable of realizing the following three requirements (1) obtaining a memory cell having a small size of 4F.sup.2 ; (2) obtaining a planar transistor which can easily be manufactured; and (3) realizing a random access function having general versatility. Moreover, the semiconductor memory device is able to hold data even during standby while a high-speed operation is being maintained, that is, the PL potential is fixed. In addition, the foregoing semiconductor memory device does not require the refreshing operation. Another semiconductor memory device is suggested which is capable of realizing a high-speed operation even if the PL operation method is employed.
All of the conventional FRAM and the apparatuses suggested by the inventors of the present invention suffers from reduction in the polarization of the ferroelectric capacitor per memory cell if the area of each ferroelectric capacitor of the memory cell is reduced owning to raising of the density. As a result, there arises a critical problem in that reduction in the voltage for reading a signal results in increase in the capacity and raising of the density being made to be difficult. Also the foregoing problem arises with the DRAM or the like. In particular, the foregoing problem becomes serious for the FRAM because it has the intrinsic problems as shown in FIGS. 2A to 2C.
FIG. 2A shows a ferroelectric capacitor. FIG. 2B shows a capacitor incorporating a ferroelectric film having a thickness, which is a half of the thickness of the film of the capacitor shown in FIG. 2A. FIG. 2C shows hysteresis characteristics of the two ferroelectric capacitors. The residual polarization of a ferroelectric material is not changed if the film thickness is reduced. In this case, the voltage resistance is lowered by a degree corresponding to the reduction in the film thickness because the coercive electric field is constant. The foregoing fact is satisfactory to realize a low-voltage operation. However, a structure having a high density and encountered reduction in the area of the capacitor of the memory cell raises a problem in that the polarization of the cell is reduced. At present, the following ferroelectric materials have been suggested: PZT, SBT and Stained BST and the like. The residual polarization is fixed to 7 to 30 .mu.C/cm.sup.2 for each material. A material of a type having a larger polarization has not been found at present. At present, only a method is effective which improves the material, for example, a method of forming the material into a single-crystal structure.
FIG. 3 is a graph in which an abscissa axis stands for design rules and an ordinate axis stands for a capacity of bitline of a FRAM and residual polarization for each cell. An assumption is made in the foregoing case that the capacity of the bitline is 512 WL/BL. The capacity is slightly reduced owning to fining of the structure (reduction in the design rule). A line indicating amount Pr of polarization required for the conventional structure indicates a minimum amount Pr of polarization required for each cell from equation as Vs=Pr/Cb on an assumption that the voltage Vs for reading a signal is 110 mV. In proportion to reduction in the capacity Cb of bitline, reduction occurs owning to fining of the structure. However, the reduction is restrained.
An assumption is made that the residual polarization of the ferroelectric material is 20 .mu.C/cm.sup.2. In this case, residual polarization, which can be obtained by a planar capacitor of a design rule of, are indicated with a line of a planar Cap. Residual polarization which can be obtained when the aspect ratio AR of the base and the height of a solid capacitor is made to be 1 to 0.7 are indicated with solid Cap (AR=1 to 0.7). Residual polarization which can be obtained when the aspect ratio of the base and the height of a solid capacitor is made to be 2 to 1.4 is indicated with solid CAP (AR=2 to 1.4). In the foregoing cases, the area of the base of the ferroelectric capacitor is 3F.sup.2 (F is a design rule).
As described above, the residual polarization for each cell, which can actually be obtained, is reduced in proportion to the square of the design rule. Therefore, the reduction in the design rule causes the residual polarization to rapidly be reduced. The foregoing graph shows a fact that there is a limitation at 256 Mb FRAM of the 0.2 .mu.m rule when the ferroelectric capacitor is formed into a planar structure. The polarization of the ferroelectric capacitors usually has anisotropy and axiality. Therefore, a satisfactory large residual polarization cannot be obtained from the solid capacitor. There has not been any report showing realization of the foregoing residual polarization by using the solid capacitor. Even if the solid cap is able to realize the foregoing residual polarization, there are limits at 1 Gb FRAM and 4 Gb FRAM, as shown in FIG. 3. The foregoing structures correspond to the conventional FRAM capable of realizing the maximum area of the base of 3F.sup.2. A cell size of 4F.sup.2, which is 50% of the conventional structure, can be realized. However, a bottom area of the base of the capacitor of F.sup.2 can be realized. The invention suggested by the inventors has a further unsatisfactory result.
Also the conventional DRAM has the cell storage amount of charges Qs which is defined such that Qs=Cs.times.(1/2)Vdd=.epsilon..times.S.div.T.times.(1/2)Vdd, where .epsilon. is a dielectric constant, S is the area of the capacitor and T is the thickness of an insulating film of the capacitor. The reduction in the power supply voltage and that in the area of the capacitor causes the cell storage amount of charges Qs be rapidly reduced. When the power supply voltage is moderately reduced regardless of reduction in the design rule, the ratio of reduction in the cell storage amount of charges Qs is equivalent to the ferroelectric memory shown in FIG. 3 in a case where T is constant. The DRAM has merit of increase in the capacity by a quantity corresponding to the reduction in the film thickness. Since the solid Cap can be realized by a BST film or the like, an expectation can be made that the structures of about 1 Gb DRAM and about 4 Gb DRAM can be realized.
However, the BST film has a limit at a thickness of about 10 nm (converted into the thickness of an oxide film of 0.1 nm). The reason for this lies in that the reduction in the thickness has a limitation and the reduction in the thickness make the dependency of the capacity on the bias voltage to be conspicuous. Specifically, the reduction in the thickness causes the capacity to be increased at low voltages. However, the capacity is not satisfactorily increased at the operating bias voltage. In an operation of reading data from cells of the DRAM, the capacity in a range for the operating point from 1/Vdd to the potential Vs for reading a signal is effective. Even if the capacity in a portion not higher than Vs is increased owning to the reduction in the thickness, there is no merit. As described above, also the conventional DRAM has a limit at 1 Gb to 4 Gb DRAM.
If the aspect ratio is increased considerably in a forcible manner, a larger capacity can be realized. However, increase in the cost and difficulty in the manufacturing process inhibits practical use. IF PZT is used instead of the BST, the lower limit cannot considerably be lowered. Basically, the high dielectric material and the ferroelectric material belong to the same material group in which atoms are moved so that the ferroelectricity is imparted or the dielectric constant is increased. Therefore, the movement of atoms has a limit. Therefore, even the high dielectric material is reduced and polarized maximally, the limit is made to be the same as that for the ferroelectric material.
To realize data retention for 10 years for the conventional EEPROM or the like, an oxide film having a thickness of about 8 nm is required because penetration of stored charges through the oxide film must be prevented. Therefore, fining of the structure has a limitation. Also a multi-level technique is employed for the EEPROM, there is a limit at 1 Gb flash memory.
To overcome the problems of the conventional FRAM, a variety of memory cells each having a self-amplifying function is suggested, as shown in FIG. 4. FIG. 4 shows correspondences of memory cells having four types of self-amplifying functions including (a), (b), (c) and (d) and the four types of problems and comparison of the cell sizes.
The memory cell shown in FIG. 4 (a) is that for a 1-transistor MFSFET transistor or a MF(M)ISFET transistor. The MFSFET transistor is a transistor incorporating gate insulating film which is a ferroelectric film. Since the foregoing transistor has the structure that the lattice constant of the ferroelectric film and that of the Si substrate are different from each other, manufacture cannot easily be performed. The MFISFET transistor is a transistor incorporating a gate insulating film which is a ferroelectric film and a buffer film made of a paraelectric material and formed at the interface with the Si substrate. The MFMISFET transistor is a transistor incorporating a ferroelectric film serving as the gate insulating film. Moreover, a conductor and a buffer film made of a paraelectric material are formed at the interface with the Si substrate. Also the foregoing transistor cannot easily be manufactured. What is worse, there are problems of the coupling ratio, leakage, erroneous writing and the like. Thus, there are a multiplicity of problems which must be overcome when the foregoing transistor is put into practical use.
The problem of the coupling ratio is caused from a fact that the dielectric constant of the ferroelectric film is usually considerably larger than that of the paraelectric film. Even if the thickness of the paraelectric film is reduced, the capacity of the ferroelectric film is undesirably increased as compared with that of the paraelectric film as shown in an equivalent circuit shown in the upper right portion of FIG. 4. Even if voltage is applied to the gate in order to write data, a major portion of the writing voltage is undesirably applied to the paraelectric film having a smaller capacity. As a result, high voltage of 7V to 15V is required to write data as compared with the FRAM capable of being operated at low voltage.
The problem of the leak is a critical problem. For example, a state of the transistor is shown in a lower right figure shown in FIG. 4. The foregoing state is realized after voltage is applied to the gate of the MFMISFET to invert the polarization of the ferroelectric film, followed by returning the voltage of the gate to 0V. Inversion of the polarization of the ferroelectric film causes positive charges to be collected to the gate portion, while negative charges are collected to a portion of the conductor disposed between the ferroelectric film and the paraelectric film adjacent to the ferroelectric film. Thus, the principle of conservation of charge in the conductor realizes a state as if the excess positive charge individually exists in the conductor. The foregoing positive charge induces a negative charges to the channel portion through the paraelectric film. The induction and non-induction of the negative charge changes the threshold voltage of the transistor so that the transistor serves as a non-destructive read enabled memory cell.
Although the foregoing function can be obtained in an ideal state, the positive charges in the conductor actually raises the potential of the inner node of the conductor. Thus, an electric field is generated between the conductor and the gate and between the conductor and the channel. If electrons are introduced into the conductor through either the ferroelectric film or the paraelectric film, there arises a problem in that information in the cell is destroyed. The preservation of data in a cell (data retention) is required for 10 years for the nonvolatile memory. The foregoing requirement can be met by a gate oxide film having a thickness of 8 nm with difficulty. The ferroelectric film or the high ferroelectric film having a small barrier height cannot meet the insurance for 10 years. As a result of previous measurements, tens of seconds have been realized at room temperature. That is, 10 years at high temperatures cannot easily be insured.
The problem of erroneous writing arises when data is written on a selected cell. In this case, also the potential of the bitline which is connected to the unselected cell inevitably varies. Depending on the method, at least 1/3 to 1/2 of the potential of the selected cell is undesirably applied to the drain terminal of the unselected cell. As a result, erroneous writing occurs. Also the flash memory encounters a similar problem. In the case of the flash memory, electric currents caused from the F-N tunneling and hot carriers are changed exponentially with respect to the applied voltage. Therefore, a critical problem does not arise. However, the ferroelectric transistor in which the polarization is inverted linearly with respect to the applied voltage encounters a critical problem.
The memory cell shown in FIG. 4A is able to theoretically realize the 4F.sup.2 size. The well potential must be controlled when data is written. In actual, the connection between the bitline and the well causes the size to be larger than the 4F.sup.2 size. At present, cells having a 6F.sup.2 size have been suggested.
A circuit shown in FIG. 4 (b) is a 2-transistor type memory cell in which the ferroelectric transistor shown in FIG. 4 (a) is connected to the bitline through a selected transistor. Among the problems of the coupling ratio, leakage, manufacturing easiness and erroneous writing, the problem of erroneous writing can be overcome by turning the selected transistor off. However, the problems of coupling ratio, leakage and manufacturing easiness cannot be overcome. What is worse, the area of the cell is 8F.sup.2 or larger, which is similar to that realized by the conventional FRAM.
A circuit shown in FIG. 4 (c) does not employ the ferroelectric FET but employs a usual transistor and a ferroelectric capacitor to overcome the problems of the leakage and the manufacturing easiness. As the transistors, a write transistor and amplified read transistors are provided. When the write transistor is turned on to apply voltage between PL-BL so as to invert the polarization. When the write transistor is turned off, writing is completed. Reading is performed by driving the PL to invert the polarization. A fact that the gate voltage of the read transistor varies depending on data "1" and "0" is used, the gate voltage is amplified by the transistor so as to read it to the bitline. The foregoing structure in which the capacity of the ferroelectric capacitor is larger than the capacity of the gate cannot, however, overcome the problem of the coupling ratio. What is worse, the size of the cell is 12F.sup.2 or larger, which is larger than that of the conventional FRAM.
A circuit shown in FIG. 4 (d) is structured such that a paraelectric capacitor is connected to the circuit shown in FIG. 4 (c). The foregoing load capacity facilitates polarization inversion reading and thus an operation free from a problem can be expected. However, a paraelectric capacitor having a capacity equal to or more than that of the ferroelectric capacitor is required. Therefore, an area larger than 16F.sup.2 is required. As a result, practical use cannot be expected because of the problem of large cost.
As described above, the conventional memory cells having the self-amplifying function have the problem in that both of the normal operation and the high density cannot be realized. Although the cell having the self-amplifying function may be applied to the DRAM, also the 2-transistor+1-capacitor structure or larger structure is required in the foregoing case. Therefore, the foregoing structure has a problem in that the size is larger than the conventional DRAM.
As described above, the conventional FRAM and the structures suggested by the inventors of the present invention have the following problem. That is, when the area of each ferroelectric capacitor of the memory cell is reduced owning to raising of the density, the residual polarization cannot be increased even if the film thickness is reduced. Therefore, the polarization of the ferroelectric capacitor for each memory cell is undesirably reduced. As a result, the voltage for reading a signal is lowered, causing increase in the capacity and raising of the density to encounter difficulties. Therefore, the FRAM has a limit of 256 Mb FRAM in a planar capacitor and a 1 Gb to 4 Gb FRAM in a solid capacitor.
Also the DRAM or the like having a limit of reduction in the thickness of the insulating film has a similar problem. The DRAM has a limit at 1 Gb to 4 Gb DRAM. The other flash memories have a limit of reduction in the thickness of the oxide film. Thus, a limit exists at a 1 Gb flash memory. That is, the conventional semiconductor memories capable of reading and writing data have the problem of the limit at 1 Gb to 4 Gb.
Also the conventional ferroelectric memories having the self-amplifying function have the essential problems of the coupling ration, leakage, manufacturing easiness and erroneous writing. To overcome the abovementioned problems, another critical problem arises in that the required area of a cell becomes 16F.sup.2 or larger.